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1. general description the TDA10023HT is a single chip dvb-c/mcns channel receiver for 4, 16, 32, 64, 128 and 256-qam modulated signals. the device interfaces directly to the if signal, which is sampled by a 10-bit a/d converter. the TDA10023HT performs the clock and the carrier recovery functions. the digital loop ?lters for both clock and carrier recovery are programmable in order to optimize their characteristics according to the current application. after baseband conversion, equalization ?lters are used for echo cancellation in cable applications. these ?lters are con?gured as t-spaced transversal equalizer or dfe equalizer, so that the system performance can be optimized according to the network characteristics. a proprietary equalization algorithm, independent of carrier offset, is achieved in order to assist carrier recovery. then a decision directed algorithm takes place, to achieve ?nal equalization convergence. the TDA10023HT chip implements two fec decoders, one for each standard. in the dvb-c mode the TDA10023HT implements a forney convolutional de-interleaver of depth 12 blocks and a reed-solomon decoder which corrects up to 8 erroneous bytes. the de-interleaver and the reed-solomon decoder are automatically synchronized thanks to the frame synchronization algorithm that uses the mpeg2 sync byte. finally descrambling according to dvb-c standard is achieved at the reed-solomon output. in the mcns mode the receiver error correction implements a soft decision trellis decoder to correct random channel errors, a randomizer, a convolutional de-interleaver of depth i = 128, 64, 32, 16, 8 and j = 1, 2, 3, 4, 8, 16 for burst protection, and a reed-solomon decoder which corrects up to 3 erroneous symbols. the de-interleaver and the reed-solomon decoder are automatically synchronized using the frame sync trailer. this device is controlled via an i 2 c-bus. TDA10023HT single chip dvb-c/mcns channel receiver rev. 01 12 april 2005 product data sheet
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 2 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 2. features n 4,16, 32, 64, 128 and 256 qam demodulator ( itu-t j.83 annex a-b and c compatible) n high performance for 256 qam especially for direct if applications n on-chip 10-bit adc n on-chip pll for crystal frequency multiplication (typically 16 mhz crystal) n digital down conversion n programmable half nyquist ?lter (roll off = 0.12, 0.13, 0.15 and 0.18) n two pwm agc outputs with programmable take-over point (for tuner and down converter control) n clock timing recovery, with programmable second order loop ?lter n variable symbol rate capability from saclk/64 to saclk/4 (with low sampling clock: saclk = 36 mhz maximum) or from saclk/128 to saclk/8 (with high sampling clock: saclk = 72 mhz maximum) n programmable anti-aliasing ?lters n full digital carrier recovery loop n carrier acquisition range up to 9 % of symbol rate n integrated adaptive equalizer (linear transversal equalizer or decision feedback equalizer) n dvb compatible differential decoding and mapping n on chip dvb-c full compliant fec decoder (de-interleaver, reed-solomon decoder and de-scrambler) n on chip mcns full compliant fec decoder (trellis demodulator, de-randomizer, de-interleaver and reed-solomon decoder) n multiple ts jqam ?lter n parallel and serial transport stream interface simultaneously n i 2 c-bus interface, for easy control 3. applications n cable set-top boxes n cable modems n cable network interface modules (nims) n multichannel multipoint distribution service (mmds) (ets 300-749) set-top boxes
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 3 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 4. quick reference data table 1: quick reference data symbol parameter conditions min typ max unit recommended operating conditions v ddd3 digital core supply voltage 1.65 1.8 1.95 v v ddd2 digital pad supply voltage 3 3.3 3.6 v t amb ambient temperature 0 - 70 c v ih high-level input voltage (including voltage on outputs in 3-state mode) all digital inputs are 5 v tolerant except xin which is 2 v tolerant 0.8v ddd3 -v ddd3 v 1.8 - 5.5 v v il low-level input voltage (including voltage on outputs in 3-state mode) all digital inputs are 5 v tolerant except xin which is 2 v tolerant 0 - 0.2v ddd3 v 0-1v v oh high-level output voltage 2.6 2.9 3.2 v v ol low-level output voltage 0 - 0.4 v i oh high-level output current v oh = v ddd2 - 0.4 v - 4.8 - - ma i ol low-level output current v ol = 0.4 v 4.2 - - ma p power dissipation qam 256 / symbol rate 6.9 mbd; f s = 29.33 mhz; cs = 150 % - 500 620 mw i tot(3v3) total current consumption for the digital and analog 3.3 v supply voltages (v ddd2 , v ddd4 , v dda3 ) qam 256 / symbol rate 6.9 mbd; f s = 29.33 mhz; cs = 150 % - 94 100 ma i tot(1v8) total current consumption for the digital and analog 1.8 v supply voltages (v ddd1 , v ddd3 , v dda2 ) qam 256 / symbol rate 6.9 mbd; f s = 29.33 mhz; cs = 150 % - 105 130 ma c i input capacitance - - 6 pf crystal oscillator characteristics v dda1 crystal analog supply voltage 1.65 1.8 1.95 v i dda1 supply current in slave mode at maximum f c - - 1.12 ma f i(slave) input frequency in slave mode 1 - 50 mhz f c output frequency 1 - 50 mhz v xin xin input level in slave mode ac coupled 400 900 - mv t start average start-up time - 500 - m s slope xin clock signal slope 25 - - v/ m s pll characteristics v dda2 analog pll supply voltage 1.6 1.8 2.0 v v ddd1 digital pll supply voltage 1.65 1.8 1.95 v i dda2 analog supply current - 1 - ma i ddd1 digital supply current - 1 - ma f ref input frequency 0.1 - 150 mhz f out output frequency 4.3 - 550 mhz t pu start-up time to power-up - - 500 m s
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 4 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver [1] gainset and cs are programmed by registers. cs must be selected as small as possible because it reduces the power consum ption. 5. ordering information 10-bit adc characteristics v dda3 analog adc supply voltage 3.0 3.3 3.6 v v ddd4 digital adc supply voltage 3.0 3.3 3.6 v v ddd1 digital adc supply voltage 1.65 1.8 1.95 v v dif differential input range v vip - v vim gainset = 0 [1] - 1 - +1 v gainset = 1 [1] - 0.5 - +0.5 v v range single-ended peak-to-peak input range (on vip) gainset = 0 [1] -2-v gainset = 1 [1] -1-v v dc dc reference level (common mode) differential input 0.5 0.5v dda3 1.8 v single-ended input 0.9 - 1.3 v r i input resistance single-ended or differential input - 7.5 - k w c i input capacitance vip or vim - 1.5 - pf f i(max) maximum input frequency cs = 11 (differential input) [1] - - 100 mhz cs = 10 (differential input) [1] - - 80 mhz cs = 01 (differential input) [1] - - 60 mhz cs = 00 (differential input) [1] - - 35 mhz cs = 10 (single-ended input) [1] - - 60 mhz f s(max) maximum sampling frequency cs = 11 [1] - - 90 mhz cs = 10 [1] - - 80 mhz cs = 01 [1] - - 60 mhz cs = 00 [1] - - 35 mhz table 1: quick reference data continued symbol parameter conditions min typ max unit table 2: ordering information type number package name description version TDA10023HT tqfp64 plastic thin quad ?at package; 64 leads; body 10 10 1.0 mm sot357-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 5 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 6. block diagram fig 1. internal block diagram 001aac555 clock recovery i 2 c-bus interface gpio agc pwm pwm timing interpolator rs decoder trellis demodulator frame sync de- randomizer de- interleaver reed solomon decoder mpeg2 ts cksum jqam filter output interface jtag de-scrambler de-interleaver decimation filters baseband conversion adc pll equalizer half nyquist carrier recovery decision differential decoder 10 8 if TDA10023HT 23 1 4 7, 24, 41 50 49 61 55 59 60 5 9 11 17 13, 51, 52, 53, 54, 56, 62, 63, 64 18 19 saclk agctun agcif scl sda sdat den oclk programmable interface serial interface psync uncor do[7:0] 37 to 40, 45 to 48 36 35 34 33 20 21 22 23 26 27 28 32 29 6 16 58 57 10 sclt enseri tck tdi trst tms tdo ctrl gpio 3 v ddd3 8, 25, 42 3 v ssd3 14, 30, 43 3 v ddd2 15, 31, 44 3 v ssd2 v ddd4 v ddd1 v ssd1 v ssa1 v dda1 v dda3 v ssa3 test iicdiv clrb vip vim n.c. v dda2 xin xout 12 saddr
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 6 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration TDA10023HT v dda1 do[0] xin do[1] xout do[2] v ssa1 do[3] saclk v ssd2 test v ddd2 v ddd3 v ssd3 v ssd3 v ddd3 agctun do[4] iicdiv do[5] agcif do[6] saddr do[7] n.c. den v ddd2 oclk v ssd2 psync clrb uncor scl n.c. sda n.c. sdat n.c. sclt v dda2 enseri v ddd4 tck v ssa3 tdi vip v ddd3 vim v ssd3 n.c. trst v dda3 tms n.c. tdo n.c. gpio n.c. v ddd2 n.c. v ssd2 v ddd1 ctrl v ssd1 001aac556 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 table 3: pin description symbol pin type [1] description v dda1 1 s crystal analog supply voltage 1.8 v xin 2 i crystal oscillator input. typically a fundamental crystal oscillator is connected between the xin and xout pins. the crystal frequency must be chosen so that the system frequency sysclk (= xin multiplying factor of the pll) equals 1.6 times the tuner output intermediate frequency: sysclk = 1.6 if. xout 3 o crystal oscillator output; typically a fundamental crystal oscillator is connected between the xin and xout pins v ssa1 4 g crystal analog ground saclk 5 o sampling clock. this output clock can be fed to an external 10-bit adc as the sampling clock. saclk can be either equal to sysclk/2 in simple sampling mode or equal to sysclk in double sampling mode. test 6 i test input pin; in normal mode, test must be grounded
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 7 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver v ddd3 7 s digital core supply voltage 1.8 v v ssd3 8 g digital core ground agctun 9 o/od first pwm encoded output signal for agc tuner. this signal is typically fed to the agc ampli?er through a single rc network. the maximum signal frequency on vagc output is xin/16. agc information can be refreshed every 512 adc samples. iicdiv 10 i iicdiv allows to select the frequency of the i 2 c-bus internal system clock, depending on the crystal frequency. internal i 2 c-bus clock is a division of xin by 4 iicdiv . agcif 11 o/od second pwm encoded output signal for agc if. this signal is typically fed to the agc ampli?er through a single rc network. the maximum signal frequency on vagc output is xin/16. agc information can be refreshed every 512 adc samples. but agcif can also be con?gured to output a pwm signal, which value can be programmed through the i 2 c-bus interface (see register pwmref, index 34h). saddr 12 i two i 2 c-bus addresses are implemented in the TDA10023HT chip. one address regarding all the TDA10023HT registers except jqam registers, and a second one dedicated to the jqam ?lter registers only. saddr is the lsb of the 2 i 2 c-bus addresses. the msbs are internally set to 000110 (all registers except jqam) and 000111 (only jqam). therefore the 2 complete i 2 c-bus addresses are (msb to lsb): 0, 0, 0, 1, 1, 0, saddr (core registers) 0, 0, 0, 1, 1, 1, saddr (jqam registers) n.c. 13 not connected v ddd2 14 s digital pad supply voltage 3.3 v v ssd2 15 g digital pad ground clrb 16 i the clrb input is asynchronous and active low, and clears the TDA10023HT. when clrb goes low, the circuit immediately enters its reset mode and normal operation will resume 4 xin falling edges later after clrb returned high. the i 2 c-bus register contents are all initialized to their default values. the minimum width of clrb at low level is 4 xin clock periods. scl 17 i i 2 c-bus clock input. scl should nominally be a square wave with a maximum frequency of 400 khz. scl is generated by the system i 2 c-bus master. sda 18 i/od sda is a bidirectional signal. it is the serial input/output of the i 2 c-bus internal block. a pull-up resistor (typically 4.7 k w ) must be connected between sda and v ddd2 (or 5 v) for proper operation (open-drain output). sdat 19 i/od sdat is equivalent to sda i/o of TDA10023HT but can be 3-stated by i 2 c-bus programming. it is actually the output of a switch controlled by parameter bypiic of register test (index 0fh). sdat is an open-drain output and therefore requires an external pull-up resistor. table 3: pin description continued symbol pin type [1] description
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 8 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver sclt 20 od sclt can be con?gured to be a control line output or to output scl input. this is controlled by parameter bypiic and ctrl_sclt of register test (index 0fh). sclt is an open-drain output and therefore requires an external pull-up resistor. enseri 21 i when high this pin enables the serial output transport stream through the boundary scan pins: trst, tdo, tck, tdi and tms (serial interface). must be set low in built-in self-test (bist) and boundary scan mode. tck 22 i/o test clock: an independant clock used to drive the tap controller in boundary scan mode. in normal mode of operation, tck must be set low. in serial stream mode, tck is the oclk output . tdi 23 i/o test data in. the serial input for test data and instruction in boundary scan mode. in normal mode of operation, tdi must be set to low. in serial stream mode, tdi is the psync output. v ddd3 24 s digital core supply voltage 1.8 v v ssd3 25 g digital core ground trst 26 i/o test reset. this active low input signal is used to reset the tap controller in boundary scan mode. in normal mode of operation, trst must be set low. in serial stream mode, trst is the uncorrectable output (uncor) and has to be connected to a pull-down resistor. tms 27 i/o test mode select. this input signal provides the logic levels needed to change the tap controller from state to state. in normal mode of operation, tms must be set low. in serial stream mode, tms is the den output. tdo 28 o test data out. this is the serial test output pin used in boundary scan mode. serial data are provided on the falling edge of tck. in serial stream mode, tdo is the data output (do). gpio 29 od gpio can be con?gured by i 2 c-bus (parameter selgpio[1:0], index 0fh) either as: a front-end lock indicator (fel) (default mode), or an active low output interrupt line (it) which can be con?gured by the i 2 c-bus interface. see registers itsel (index 32h/33h) and itstat (index 3eh/3fh), or a control output pin programmable by i 2 c-bus (parameter ctrl_gpio, index 1eh) gpio is an open-drain output and therefore requires an external pull-up resistor. v ddd2 30 s digital pad supply voltage 3.3 v v ssd2 31 g digital pad ground ctrl 32 od ctrl is a control output pin programmable by i 2 c-bus parameter ctrl of register control (index 1eh). ctrl is open-drain output, and therefore requires an external pull-up resistor. table 3: pin description continued symbol pin type [1] description
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 9 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver uncor 33 o in dvb mode, uncorrectable transport stream packet. this output signal is high when the provided packet is uncorrectable (during the 188 bytes of the packet). the uncorrectable packet is not affected by the reed-solomon decoder, but the msb of the byte following the sync byte is forced 1 for the mpeg2 process: error ?ag indicator (if rsi and iei are set low in the i 2 c-bus table). in mcns mode, uncorrectable reed-solomon blocks. this output signal is high when the provided block is uncorrectable (during the entire block). the uncorrectable block is not affected by the reed-solomon decoder. psync 34 o pulse synchro output. this output signal goes high when the sync byte (47h) is provided (in dvb or mcns modes), then it goes low until the next sync byte. also by default (register tsout, index 1eh), psync is forced low when uncor pin goes high. oclk 35 o output clock output. oclk is the output clock for the do[7:0] data outputs. oclk is internally generated depending on which interface is selected. den 36 o data enable (in dvb/mcns modes). this output signal is high when there is a valid data on output bus do[7:0]. also by default (register tsout, index 1eh), den is forced low when uncor pin goes high. do[7:0] 37,38, 39,40, 45,46, 47,48 o data output bus. these 8-bit parallel data are the outputs of the TDA10023HT after demodulation and fec (dvb or mcns) decoder. when one of the 3 possible parallel interfaces (a/b/c) is selected (parameter intpsel = 00/01/10, index 20h) then do[7:0] is the transport stream output. when the serial interface is selected (parameter intpsel = 11, index 20h) then the serial output is on pin do[0]. also by default (register tsout, index 1eh), in dvb or mcns mode, the ts data is forced to the null ts ffh when the uncor pin goes high. v ddd3 41 s digital core supply voltage 1.8 v v ssd3 42 g digital core ground v ddd2 43 s digital pad supply voltage 3.3 v v ssd2 44 g digital pad ground v ssd1 49 g ground return for the digital switching circuitry (adc and pll) v ddd1 50 s supply voltage for the digital switching circuitry 1.8 v (adc and pll) n.c. 51 not connected n.c. 52 not connected n.c. 53 not connected n.c. 54 not connected v dda3 55 s supply voltage for the analog circuits 3.3 v (adc) n.c. 56 not connected table 3: pin description continued symbol pin type [1] description
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 10 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver [1] all inputs (i) are ttl, 5 v tolerant (except xin, vip and vim). od are open-drain outputs, so they must be connected to a pull-up resistor to v ddd2 (3.3 v) or 5 v. all outputs are 4 ma drive, 5 v tolerant. 8. limiting values vim 57 i negative input to the a/d converter. this pin is dc biased to half-supply voltage through an internal resistor divider (2 20 k w resistors). in order to stay in the range of the adc, |v vip - v vim | should remain between the input range corresponding to the gainadc register (index 1bh - default value = 2 v). vip 58 i positive input to the a/d converter. this pin is dc biased to half-supply voltage through an internal resistor divider (2 20 k w resistors). in order to stay in the range of the adc, |v vip - v vim | should remain between the input range corresponding to the gainadc register (index 1bh - default value = 2 v). v ssa3 59 g ground return for analog circuits (adc) v ddd4 60 s digital supply voltage for the switching circuitry 3.3 v (adc) v dda2 61 s analog supply voltage 1.8 v (pll) n.c. 62 not connected n.c. 63 not connected n.c. 64 not connected table 3: pin description continued symbol pin type [1] description table 4: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddd3 digital core supply voltage - 0.5 +1.98 v v ddd2 digital pad supply voltage - 0.5 +3.6 v xin xin input signal - 0.5 +2.0 v v i dc analog input voltage - 0.5 v dd + 0.5 v v i dc input voltage - 0.5 +5.5 v i i dc input current - 20 ma t lead lead temperature - 300 c t stg storage temperature - 65 +150 c t amb ambient temperature 0 70 c t j junction temperature - 150 c
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 11 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 9. application information 9.1 general block diagram 9.2 typical application fig 3. general block diagram 5 001aac557 saddr scl sclt ctrl i 2 c-bus interfaces programmable output inputs xin xout power supplies sda sdat gpio v ddd2 v ddd1 agctun agcif saclk do[7:0] den oclk psync uncor vim iicdiv vip clrb test enseri 8 3 v ddd4 3 v dda1 v ssa1 3 v dda3 3 v dda2 v ssa3 v ssd3 v ssd1 v ddd3 v ssd2 boundary scan serial output TDA10023HT (1) first output1 can be either a parallel output mode a, a parallel output mode b, a parallel output mode c, or a serial output (programmable interface). (2) second output2 is a serial output (serial interface). fig 4. front-end receiver schematic 001aac558 i 2 c-bus i 2 c-bus tuner output1 (1) output2 (2) analog circuitry agc2 circuitry tuner if rf input TDA10023HT den oclk psync uncor vip vim sclt, sdat scl, sda agcif agctun xin xout tck (oclk) tdi (psync) trst (uncor) tms (den) tdo (do) do [ 7:0 ] agc1 circuitry
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 12 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 9.3 crystal oscillator 9.4 external agc circuitry (1) typical crystal is on fundamental frequency (typically 16 mhz). (2) values of passive components are dependant on crystal manufacturer (typically c1 = c2 = 56 pf). fig 5. typical crystal connection 001aac559 23 xtal c2 xout xin c1 TDA10023HT (1) r and c are chosen to verify sr/1024 < f c << xin/16 with r = 1.5 k w and c = 1 nf, f c = 100 khz. fig 6. external agc connection 001aac560 r 9 11 c to tuner/if agctun/ agcif TDA10023HT
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 13 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 9.5 external pll and adc connections fig 7. pll and adc connections 0.1 m f 0.1 m f 61 60 59 58 57 55 50 49 TDA10023HT 1 w 10 nf 10 m f 1.8 v 1 w 10 nf 10 m f 3.3 v 1 w 10 nf 10 m f 3.3 v 1 w 10 nf 10 m f 1.8 v v ddd1 v ssd1 v dda2 v ddd4 v ssa3 vip vim vinp vinm v dda3 001aac561
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 14 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 10. package outline fig 8. package outline sot357-1 (tqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.08 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot357-1 137e10 ms-026 00-01-19 02-03-14 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale tqfp64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm sot357-1
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 15 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 11. soldering 11.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 11.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 11.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 16 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 11.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 11.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 5: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 17 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 18 of 20 philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 12. revision history table 6: revision history document id release date data sheet status change notice doc. number supersedes TDA10023HT_sds_1 20050412 product data sheet - 9397 750 14559 -
philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 9397 750 14559 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 01 12 april 2005 19 of 20 13. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 14. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 15. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 16. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 april 2005 document number: 9397 750 14559 published in the netherlands philips semiconductors TDA10023HT single chip dvb-c/mcns channel receiver 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 5 ordering information . . . . . . . . . . . . . . . . . . . . . 4 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 9 application information. . . . . . . . . . . . . . . . . . 11 9.1 general block diagram . . . . . . . . . . . . . . . . . . 11 9.2 typical application. . . . . . . . . . . . . . . . . . . . . . 11 9.3 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 12 9.4 external agc circuitry . . . . . . . . . . . . . . . . . . 12 9.5 external pll and adc connections . . . . . . . . 13 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 11 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 11.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 11.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 11.5 package related soldering information . . . . . . 16 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 13 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 14 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16 contact information . . . . . . . . . . . . . . . . . . . . 19

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